MRF89XA-I/MQ【PDF 137/140 页】TXRX ISM SUB-GHZ ULP 32QFN

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MRF89XA

INDEX

A

Absolute Maximum Ratings .............................................. 103

Architecture Description ...................................................... 20

B

Bit Synchronizer .................................................................... 7

Block Diagrams

Detailed....................................................................... 12

MRF89XA Simplified Functional ................................... 8

Power Supply.............................................................. 14

C

Channel Filters .................................................................... 16

CLKOUT Output (CLKOUT Pin) ......................................... 16

Configuration Control/Status Register Map ........................ 54

Configuration/Control/Status Register Description ............. 28

Customer Change Notification Service ............................. 135

Customer Notification Service........................................... 135

Customer Support ............................................................. 135

D

DATA Pin ............................................................................ 19

Digital Pin Configuration vs. Chip Mode ............................. 18

E

Electrical Characteristics................................................... 103

Current Consumption................................................ 104

Digital I/O Pin Input Specifications............................ 105

PLL Parameters AC Characteristics ......................... 105

Receiver AC Characteristics ..................................... 106

SPI Timing Specification ........................................... 107

Switching Times and Procedures ............................. 108

Transmitter AC Characteristics ................................. 107

Errata .................................................................................... 5

F

Features

Digital Data Processing................................................. 7

Frequency Synthesizer Block ............................................. 16

Frequency Synthesizer Description .................................... 16

FSK Receiver Setting.......................................................... 22

G

General Configuration Register Details .............................. 30

H

Hardware Description ................................................... 11, 93

I

I(t), Q(t) Overview ............................................................... 20

Internet Address................................................................ 135

Interpolation Filter ............................................................... 15

IRQ Pins and Interrupts ...................................................... 19

L

LO Generator ...................................................................... 17

Low Noise Amplifier (with First Mixer)................................. 15

M

Memory Map ....................................................................... 26

Microchip Internet Web Site .............................................. 135

O

OOK Receiver Setting......................................................... 22

P

Packaging

Details....................................................................... 129

Packaging Information ...................................................... 129

Phase-Locked Loop Architecture........................................ 17

Pin Descriptions.................................................................. 13

Pins

CLKOUT ..................................................................... 17

CSCON....................................................................... 23

CSDAT ....................................................................... 23

DATA .......................................................................... 19

OSC1.......................................................................... 16

OSC2.......................................................................... 16

PLOCK ....................................................................... 17

Reset .......................................................................... 15

RFIO ..................................................................... 11, 15

PLL Lock Pin ...................................................................... 17

P OUT and I DD vs. PA Setting ............................................ 120

Power Amplifier................................................................... 15

Power Supply Pin Details ................................................... 14

Power-Saving Modes.......................................................... 17

R

Read Bytes Sequence ........................................................ 25

Read Register Sequence.................................................... 24

Reader Response............................................................. 136

Receiver Architecture ......................................................... 21

Recommended Operating Conditions............................... 103

Recommended PA Biasing and Output Matching .............. 97

Reference Oscillator Pins (OSC1/OSC2) ........................... 16

Register Map ...................................................................... 54

Registers

Bit Rate Set Register (BRSREG) ............................... 32

Clock Output Control Register (CLKOUTREG) .......... 50

Data and Modulation Configuration Register

(DMODREG) ...................................................... 31

FIFO Configuration Register (FIFOCREG)................. 33

FIFO CRC Configuration Register (FCRCREG)......... 53

FIFO Transmit and Receive Interrupt Request

Configuration Register (FTXRXIREG)................ 38

FIFO Transmit PLL and RSSI Interrupt Request

Configuration Register (FTPRIREG) .................. 40

Filter Configuration Register (FILCREG).................... 42

Floor Threshold Control Register (FLTHREG) ........... 33

Frequency Deviation Control Register (FDEVREG)... 32

General Configuration Register (GCONREG) ............ 30

Node Address Set Register (NADDSREG) ................ 51

OOK Configuration Register (OOKCREG) ................. 46

P1 Counter Set Register (P1CREG) .......................... 34

P2 Counter Set Register (P2CREG) .......................... 36

Packet Configuration Register (PKTCREG) ............... 52

Payload Configuration Register (PLOADREG) .......... 51

Polyphase Filter Configuration Register

(PFCONREG)..................................................... 43

Power Amplifier Control Register (PACREG)............. 37

R1 Counter Set Register (R1CREG) .......................... 34

R2 Counter Set Register (R2CREG) .......................... 35

Reserved Register (RESVREG)................................. 45

RSSI Status Read Register (RSTSREG) ................... 45

RSSI Threshold Interrupt Request Configuration

Register (RSTHIREG) ........................................ 41

S1 Counter Set Register (S1CREG) .......................... 35

S2 Counter Set Register (S2CREG) .......................... 36

? 2010–2011 Microchip Technology Inc.

Preliminary

DS70622C-page 137

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